Ion implantation is a standard technique for introducing conductivity-altering dopant materials into semiconductor wafers. In a conventional ion implantation system, a desired dopant material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy, and the ion beam is directed at the surface of the wafer. The energetic ions in the beam penetrate into the bulk of the semiconductor material and are embedded into the crystalline lattice of the semiconductor material. Following ion implantation, the semiconductor wafer is annealed to activate the dopant material. Annealing involves heating the semiconductor wafer to a prescribed temperature for a prescribed time.
A well-known trend in the semiconductor industry is toward smaller, higher speed devices. In particular, both the lateral dimensions and the depths of features in semiconductor devices are decreasing. State of the art semiconductor devices require junction depths less than 1000 angstroms and may eventually require junction depths on the order of 200 angstroms or less.
The implanted depth of the dopant material is determined by the energy of the ions implanted into the semiconductor wafer. Shallow junctions are obtained with low implant energies. However, the annealing process that is used for activation of the implanted dopant material causes the dopant material to diffuse from the implanted region of the semiconductor wafer. As a result of such diffusion, junction depths are increased by annealing. To counteract the increase in junction depth produced by annealing, the implant energy may be decreased, so that a desired junction depth after annealing is obtained. This approach provides satisfactory results, except in the case of very shallow junctions. A limit is reached as to the junction depth that can be obtained by decreasing implant energy, due to the diffusion of the dopant material that occurs during annealing. In addition, ion implanters typically operate inefficiently at very low implant energies.
Rapid thermal processing can be used to minimize the diffusion that occurs during annealing. However, significant changes to the annealing process, such as reduced annealing temperatures, would reduce the amount of dopant material activated and would thereby adversely affect the operating characteristics of the semiconductor device.
The current state of the art for low energy boron implants, which are annealed at a typical temperature of 1050.degree. C. for good electrical activation, provides junction depths in excess of 1050 angstroms. Prior art attempts to reduce the junction depth for low energy boron have met with limited success. The process of transient enhanced diffusion (TED), wherein silicon interstitial enhance diffusion of boron, has been proposed to explain the difficulty in achieving ultra shallow junctions. See, for example, M. I. Current et al, "20 da eV (200 eV) to 10 keV Boron Implantation and Rapid Thermal Annealing of Si(100): A SIMS and TEM Study", 4th International Workshop-Meas., Char. & Modeling of Ultra-Shallow Doping Profiles, April 1997, pages 41.1 to 41.12 and E.J. H. Collart et al "Characterization of Low Energy (100 eV10 keV) Boron Ion Implantation", 4th International Workshop-Meas., Char. & Modeling of Ultra-Shallow Doping Profiles, April 1997, pages 6.1 to 6.9.
It was reported by A. Agarwal et al in "Boron Enhanced Diffusion of Boron: The Limiting Factor for Ultra-Shallow Junctions", IEDM 97, 1997, pages 467-470, that boron enhanced diffusion (BED) is a limiting factor for creating shallow junctions with boron implants at energies below 1 keV annealed at 1050.degree. C. for 10 seconds. It was reported that no matter how low in energy the boron was implanted, and even for a 1 eV molecular beam epitaxy deposition, a junction depth greater than 1000 angstroms resulted. Boron enhanced diffusion was reported to be caused by the formation of a SiB.sub.4 layer which injects interstitials into the silicon and drives this enhanced diffusion. This boron enhanced diffusion was reported to be the limiting factor in fabricating boron shallow junctions.
None of the prior art known to applicant has provided a satisfactory process for fabricating ultra shallow junctions of selected junction depth and sheet resistance, particularly where the required junction depth cannot be obtained simply by reducing the implant energy. Accordingly, a need exists for improved methods for fabricating ultra-shallow junctions in semiconductor wafers and for improved methods for activating implanted dopant material in semiconductor wafers by thermal processing.